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Figure 7: I/O Write waveforms
Table 22: I/O write timing
Cycle Time Mode
250ns
120ns
100ns
80ns
Item
Symbol
IEEEE
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
NA
NA
NA
NA
NA
NA
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
Address Setup before IOWR
Address Hold following IOWR
CE setup before IOWR
CE Hold following IOWR
REG setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from Addr.
IOIS16 Delay Rising from Addr.
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tDVIWH
tIWHDX
tIWLIWH
tAVIWL
tIWHAX
tELIWL
tIWHEH
tRGLIWL
tIWHRGH
tAVISL
tAVISH
60
30
165
70
20
5
20
5
0
35
35
20
10
70
25
20
5
20
5
0
(2)
(2)
20
5
65
25
10
5
10
5
0
(2)
(2)
15
5
55
15
10
5
10
5
0
(2)
(2)
1.
2.
D IN signifies data provided by the system to the CompactFlash TM Memory Card.
– IOIS16 and – INPACK are not supported in this mode.
6.4 True IDE Mode
The timing waveforms for True IDE mode and True IDE DMA mode of operation in this section are drawn using the
conventions in the ATA-4 specification, which are different than the conventions used in the PCMCIA specification
and earlier versions of this specification. Signals are shown with their asserted state as High regardless of
whether the signal is actually negative or positive true. Consequently, the – IORD, the
-IOWR and the – IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 22 of 102
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